3.0 Circuit Descriptions
3.2 PCM Channel
RS8953B/8953SPB
HDSL Channel Unit
shows the phase relationship between TMSYNC and MSYNC
when TFRAME_LOC is equal to 0.
illustrates the progression of
MSYNC with increasing bit and frame delays.
NOTE:
MSYNC can optionally mark the start of every PCM frame (bit 0, all
frames) by setting MF_LEN equal to 1 frame per multiframe.
Figure 3-5. PCM Transmit Sync Timing
TCLK
TMSYNC
TFRAME_LOC=0, TMF_LOC=0
MSYNC
FRAME_LEN[X]
TSER
INSDAT
0
1
2
X
Sample PCM Bit 0 or F-bit, of Frame 0
NOTE(S):
TCLK falling edge samples and rising edge outputs shown per TCLK_SEL = 00
Figure 3-6. PCM Transmit Data Timing
TMSYNC
0 1M
TFRAME_LOC[M] = MSYNC Bit Delay
0 1 N
MSYNC
FRAME_LEN[X] = PCM Frame Length
PCM
Bit
PCM
Frame
PCM
Mframe
0
X
MF_LEN[Y] = PCM Multiframe Length
Frame 0
Frame Y
MF_CNT[Z] = Mframes per 6 ms period
Mframe 0
Mframe 1
Mframe Z
TMF_LOC[N] = MSYNC Frame Delay
3.2.1.1 Transmit
Synchronization
Alignment of transmit PCM data in relation to MSYNC determines whether PCM
and HDSL frames are synchronously mapped. The RS8953B does not examine
transmit data for T1, E1, or application framing patterns. Therefore, the system
must apply PCM data aligned to MSYNC when synchronous mapping is desired.
If the system applies PCM bit 0, frame 0 coincident with MSYNC, then the
transmit router guarantees that each PCM timeslot placed in the TFIFO will be
aligned and mapped into a specific HDSL payload byte. In addition, timeslots
from the first PCM frame are mapped to payload bytes in the first HDSL payload
block, and the start of a PCM multiframe is aligned with the start of an HDSL
frame.
3-6
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
