3.0 Circuit Descriptions
3.2 PCM Channel
RS8953B/8953SPB
HDSL Channel Unit
3.2.2 PCM Receive
The PCM receive formatter shown in
constructs the serial data (RSER)
output according to receive combination table settings and the frame format
defined by the PCM Formatter Registers (see
The PCM receiver
operates on the clock edge selected by RCLK_SEL [CMD_2; addr 0xE6] and
references the PCM receive timebase and RSER frame location to the alignment
provided by the master HDSL channel’s receive 6 ms frame. Therefore, the
position of bit 0, frame 0 output on RSER, is slaved to the HDSL receiver
selected as master by MASTER_SEL [CMD_5; addr 0xE9]. The RSER timing
relationship with respect to PCM 6 ms sync is shown in
PCM 6 ms
sync is created from the HDSL 6 ms frame delayed by the programmed
RFIFO_WL [addr 0xCD] value, as shown in
Figure 3-9. PCM Receive Block Diagram
BER_SEL
DBANK 1
BER Meter
TSER
DBANK 2
DBANK 3
RSER
SIG Table
RFIFO 1
RFIFO 2
PP_LOOP
RFIFO 3
Combine Table
TMSYNC
RMSYNC
Frame
Delay
PCM Receive Timebase
Bit
Delay
MF
Length
Frame
Length
MF
Count
RFIFO_WL
CH1 RSYNC
CH2 RSYNC
CH3 RSYNC
DPLL RCLK
EXCLK
TCLK
= Command Register Bit
RCLK_INV
RCLK_SEL
FROM CH1 RMAP
FROM CH2 RMAP
FROM CH3 RMAP
DROP
RX_RST
MASTER_SEL
RCLK
3-10
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
