CY62128EV30 MoBL
®
Capacitance
Parameter
C
IN
C
OUT
Parameter
JA
JC
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
TSOP I
33.01
3.42
SOIC
48.67
25.86
STSOP
32.56
3.59
Unit
°C/W
°C/W
Figure 4. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
30 pF
INCLUDING
JIG AND
SCOPE
R2
GND
Rise Time = 1 V/ns
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN
EQUIVALENT
OUTPUT
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
R
TH
V
3.0V
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for data retention
Data retention current
V
CC
= 1.5 V,
CE
1
> V
CC
0.2 V or CE
2
< 0.2 V,
V
IN
> V
CC
0.2
V or V
IN
< 0.2 V
Industrial
Conditions
Min
1.5
–
Typ
–
–
Max Unit
–
3
V
µA
t
CDR
t
R
Chip deselect to data retention time
Operation recovery time
0
45
–
–
–
–
ns
ns
Note
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
11. Chip enables (CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
12. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 µs or stable at V
CC(min)
100 µs.
Document #: 38-05579 Rev. *I
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