CY62128EV30 MoBL
®
Switching Waveforms
(continued)
Figure 9. Write Cycle No. 2 CE1 or CE2 controlled
t
WC
ADDRESS
t
SCE
t
SA
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
CE
Figure 10. Write Cycle No. 3 WE controlled, OE LOW
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
SD
DATA I/O
NOTE 30
t
HZWE
DATA VALID
t
PWE
t
HA
t
HD
t
LZWE
Truth Table
CE
1
H
X
L
L
L
CE
2
X
L
H
H
H
WE
X
X
H
L
H
OE
X
X
L
X
H
Inputs/Outputs
High Z
High Z
Data out
Data in
High Z
Mode
Deselect/power-down
Deselect/power-down
Read
Write
Selected, outputs disabled
Power
Standby (I
SB
)
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Notes
26. CE is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
27. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
28. Data I/O is high impedance if OE = V
IH
.
29. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
30. During this period, the I/Os are in output state. Do not apply input signals.
31. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document #: 38-05579 Rev. *I
Page 8 of 15
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