CY7C024/0241
CY7C025/0251
Switching Characteristics
Over the Operating Range
7C024/0241–15
7C025/0251–15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE[11]
t
DOE
t
HZOE[12, 13,
14]
7C024/0241–25
7C025/0251–25
Min.
25
Max.
7C024/0241–35
7C025/0251–35
Min.
35
Max.
7C024/0241–55
7C025/0251–55
Min.
55
Max.
Unit
ns
55
3
ns
ns
55
25
3
25
3
ns
ns
ns
ns
ns
25
0
ns
ns
55
55
55
35
35
0
0
35
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
0
70
45
ns
ns
ns
ns
Description
Read Cycle Time
Address to Data Valid
Output Hold From
Address Change
CE LOW to Data Valid
OE LOW to Data Valid
Min.
15
Max.
15
3
15
10
3
10
3
10
0
15
15
15
12
12
0
0
12
10
0
10
0
30
25
0
25
20
20
0
0
20
15
0
0
3
3
3
25
3
25
13
3
15
3
15
0
25
25
35
30
30
0
0
25
15
0
15
0
50
35
35
35
20
20
t
LZOE[12, 13, 14]
OE Low to Low Z
OE HIGH to High Z
t
LZCE[12, 13, 14]
CE LOW to Low Z
t
HZCE[12, 13,
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write
End
Address Hold From
Write End
Address Set-Up to
Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read
Data Valid
20
t
PU[14]
t
PD[14]
t
ABE[11]
t
WC
t
SCE[11]
t
AW
t
HA
t
SA[11]
t
PWE
t
SD
t
HD
t
HZWE[13, 14]
t
LZWE[13, 14]
t
WDD[15]
t
DDD[15]
25
35
WRITE CYCLE
20
60
35
Notes:
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
11. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
12. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
13. Test conditions used are Load 3.
14. This parameter is guaranteed but not tested.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document #: 38-06035 Rev. *B
Page 7 of 20
CYPRESS [ CYPRESS SEMICONDUCTOR ]
