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CY7C024-55AC 参数 Datasheet PDF下载

CY7C024-55AC图片预览
型号: CY7C024-55AC
PDF下载: 下载PDF文件 查看货源
内容描述: 4K X 16/18和8K X 16/18双端口静态RAM与SEM , INT , BUSY [4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY]
分类和应用:
文件页数/大小: 20 页 / 771 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C024/0241
CY7C025/0251
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)
t
RC
ADDRESS
t
OHA
DATA OUT
t
AA
DATA VALID
7C024–14
t
OHA
PREVIOUS DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)
CE and
LB or UB
OE
t
ACE
t
HZCE
t
DOE
t
HZOE
t
LZOE
DATA VALID
t
LZCE
t
PU
DATA OUT
I
CC
CURRENT
I
SB
t
PD
7C024–15
Read Cycle No. 3 (Either Port)
t
RC
ADDRESS
t
AA
UB or LB
t
HZCE
t
LZCE
t
ABE
CE
t
ACE
t
LZCE
DATA OUT
t
HZCE
t
OHA
7C024–16
Notes:
19. R/W is HIGH for read cycles
20. Device is continuously selected CE = V
IL
and UB or LB = V
IL
. This waveform cannot be used for semaphore reads.
21. OE = V
IL
.
22. Address valid prior to or coincident with CE transition LOW.
23. To access RAM, CE = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
Document #: 38-06035 Rev. *B
Page 9 of 20