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CY7C1352B-100AC 参数 Datasheet PDF下载

CY7C1352B-100AC图片预览
型号: CY7C1352B-100AC
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×18 Pipilined SRAM与NOBL架构 [256K x 18 Pipilined SRAm with NoBL Architecture]
分类和应用: 静态存储器
文件页数/大小: 12 页 / 190 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied
.................................................. −55°C
to +125°C
Supply Voltage on V
DD
Relative to GND
.........−0.5V
to +4.6V
DC Voltage Applied to Outputs
in High Z State
[7]
.....................................−0.5V
to V
DDQ
+ 0.5V
DC Input Voltage
[7]
..................................−0.5V
to V
DDQ
+ 0.5V
CY7C1352B
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Com’l
Ambient
Temperature
[8]
0
°
C to +70
°
C
V
DD
/V
DDQ
3.3V ± 5%
Electrical Characteristics
Over the Operating Range
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
I
OZ
I
CC
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[7]
Test Conditions
Min.
3.135
3.135
Max.
3.465
3.465
0.4
Unit
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
DD
= Min., I
OH
= –4.0 mA
[9]
V
DD
= Min., I
OL
= 8.0 mA
[9]
2.4
2.0
−0.3
V
DD
+
0.3V
0.8
5
30
5
400
375
350
300
250
200
90
80
70
60
50
40
5
Input Load Current
Input Current of MODE
GND
V
I
V
DDQ
−5
−30
−5
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
Output Leakage Current GND
V
I
V
DDQ,
Output Disabled
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
I
SB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
I
SB2
Automatic CE Power-
Down Current—CMOS
Inputs
Automatic CE Power-
Down Current—CMOS
Inputs
Max. V
DD
, Device Deselected, V
IN
All speed grades
0.3V or V
IN
> V
DDQ
– 0.3V,
f=0
Max. V
DD
, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
I
SB3
80
70
60
50
40
30
mA
mA
mA
mA
mA
mA
Shaded areas contain advance information.
Notes:
7. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
8. T
A
is the case temperature.
9. The load used for V
OH
and V
CL
testing is shown in part (b) of A/C Test Loads and Waveforms.
6