PRELIMINARY
Switching Waveforms
Read/Write/Deselect Sequence
DESELECT
WRITE
SUSPEND
READ
READ
CY7C1352B
DESELECT
CLK
t
CH
t
CL
t
CYC
t
CENS
t
CENH
CEN
t
AS
t
AH
CEN HIGH blocks
all synchronous inputs
RA3
RA4
WA5
RA6
RA7
ADDRESS
RA1
WA2
WE &
BWS
[1:0]
t
WS
t
WH
t
CES
t
CEH
CE
t
DS
t
DH
D2
In
t
CHZ
t
DOH
Q3
1a
Out
Q4
Out
D5
In
Q6
Out
t
CHZ
Q7
Out
t
CLZ
t
DOH
Q1
1a
Out
Data-
In/Out
Device
originally
deselected
t
CO
The combination of WE & BWS
[1:0]
defines a write cycle (see Write Cycle Description table).
CE is the combination of CE
1
, CE
2
, and CE
3
. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
= DON’T CARE
= UNDEFINED
9
DESELECT
WRITE
READ
READ
READ
CYPRESS [ CYPRESS SEMICONDUCTOR ]
