CY7C4255
CY7C4265
Pin Configurations
TQFP/STQFP
Top View
Q
Q
48
47
D
15
D
14
D
13
D
12
1
2
14
13
GND
46
45
3
4
Q
12
Q
V
44
43
42
41
11
D
D
5
6
7
8
11
CC
10
CY7C4255
CY7C4265
Q
10
D
9
Q
9
D
D
8
7
6
GND
40
39
9
10
Q
8
D
D
D
D
D
D
38
37
36
11
12
13
Q
7
5
Q
6
4
Q
5
3
35
34
14
15
GND
2
Q
4
1
D
0
33
V
CC
16
4255–3
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
Functional Description (continued)
The CY7C4255/65 provides five status pins. These pins are decod-
ed to determine one of five states: Empty, Almost Empty, Half Full,
Almost Full, and Full. The Half Full flag shares the WXO pin. This flag
is validinthestand-alone andwidth-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO) information that is used to signal the next FIFO
when it will be activated.
flags become synchronous if the VCC/SMODE is tied to VSS
.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65-10
7C4255/65-15
7C4255/65-25
7C4255/65-35
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
100
8
66.7
10
15
4
40
15
25
6
28.6
20
35
7
10
3
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0.5
8
1
1
2
10
45
50
15
45
50
20
45
50
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
45
50
CY7C4255
8K x 18
CY7C4265
Density
16K x18
Package
64-pin TQFP, STQFP 64-pin TQFP, STQFP
Document #: 38-06004 Rev. *B
Page 2 of 22
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