DS2167/DS2168
both X and Y interfaces, the device enters a low-power
standby mode. The DS2167 will power-up within
200 ms after the X or Y side is reactivated (IPD=0) from
standby. The DS2168 requires an external hardware re-
set after IPD is cleared to “wake-up” from standby. The
DS2168 will power-up immediately after the low-high
transition on RST.
ALRST resets the algorithm coefficients for the selected
channel to their initial values. ALRST will be cleared by
the device when the algorithm reset is complete.
The bypass feature is enabled when BYP is set and IPD
is clear. During bypass, no expansion or compression of
data occurs. This feature allows the user to interchange
timeslots under control of the timeslot registers. Bypass
operates on byte-wide slots when CP/EX=1, on nibble-
wide slots when CP/EX=0.
A-law (µ/A=0) or
µ-law
PCM (µ/A=1) coding is indepen-
dently selected for the X and Y side interfaces by bit
µ/A.
If BYP and IPD are clear, CP/EX determines if input data
is to be compressed or expanded.
TIMESLOT ASSIGNMENT
On-chip counters establish when PCM data I/O occurs
and are programmed via the timeslot registers. Timeslot
size (4 or 8 bits wide) is determined by the state of
CP/EX. Timeslots are counted from the rising edge of
FSX and FSY.
ADDRESS/COMMAND BYTE
Figure 3
(MSB)
–
SYMBOL
–
X/Y
X/Y
POSITION
ACB.7
ACB.6
A5
A4
A3
A2
A1
(LSB)
a0
NAME AND DESCRIPTION
Reserved, must be 0 for proper operation.
X/Y Channel Select.
0 = Update channel Y characteristics.
1 = Update channel X characteristics.
MSB of Device Address.
A5
A4
A3
A2
A1
A0
ACB.5
ACB.4
ACB.3
ACB.2
ACB.1
ACB.0
LSB of Device Address.
022698 6/15
DALLAS [ DALLAS SEMICONDUCTOR ]
