EBD11UD8ADDA-E
Byte No. Function described
28
Bit7
Bit6
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
0
Bit5
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
1
0
Bit4
1
1
0
1
0
0
0
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
Bit3
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
0
1
1
1
0
Bit2
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
1
1
1
0
Bit1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
1
0
Bit0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
Hex value
30H
3CH
48H
50H
2AH
2DH
80H
75H
90H
75H
90H
45H
50H
45H
50H
00H
3CH
41H
48H
4BH
30H
2DH
32H
55H
75H
00H
00H
42H
F9H
24H
7FH
7FH
FEH
00H
Comments
12ns
15ns
18ns
20ns
42ns
45ns
512M bytes
0.75ns
0.9ns*
*1
Minimum row active to row active delay
(tRRD)
0
-6B
-7A, -7B
0
0
0
0
0
1
0
1
0
1
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
Minimum active to precharge time
(tRAS)
-6B
-7A, -7B
Module rank density
Address and command setup time
before clock (tIS)
-6B
-7A, -7B
Address and command hold time after
clock (tIH)
-6B
-7A, -7B
29
30
31
32
1
33
0.75ns
0.9ns*
*1
1
34
Data input setup time before clock (tDS)
0
-6B
-7A, -7B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
Data input hold time after clock (tDH)
-6B
-7A, -7B
Superset information
Active command period (tRC)
-6B
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
-7A, -7B
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
-7A, -7B
Data hold skew (tQHS)
-6B
-7A, -7B
Superset information
SPD Revision
Checksum for bytes 0 to 62
-6B
-7A
-7B
0.45ns
0.5ns*
*1
1
35
0.45ns
0.5ns*
*1
1
36 to 40
41
Future use
60ns
*1
65ns*
72ns
1
42
*1
75ns*
12ns*
1
1
43
44
450ps
*1
500ps*
550ps
1
45
*1
750ps*
1
46 to 61
62
63
Future use
66
249
36
64
65
66
67 to 71
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Elpida Memory
Data Sheet E0603E10 (Ver. 1.0)
6