EDD2532DGBH-TT
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
Parameter
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write command
delay
(CL = 3)
Burst stop command to DQ high-Z
(CL = 3)
Read command to write command delay
(to output all data)
(CL = 3)
Pre-charge command to high-Z
(CL = 3)
Write command to data in latency
Write recovery
DM to data in latency
Mode register set command cycle time
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTZ
tRWD
tHZP
tWCD
tWR
tDMD
tMRD
6.0ns
min.
4 + BL/2
BL/2
3 + BL/2
3
3
3 + BL/2
3
1
3
0
2
20
14
2
1
2
max.
7.5ns
min.
3 + BL/2
BL/2
2 + BL/2
3
3
3 + BL/2
3
1
2
0
2
16
11
2
1
2
max.
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Self-refresh exit to non-column command tSREX
Auto-refresh period
Power-down entry
Power-down exit to command input
CKE minimum pulse width
tRFC
tPDEN
tPDEX
tCKE
Preliminary Data Sheet E1201E20 (Ver. 2.0)
10
ELPIDA [ ELPIDA MEMORY ]
