EDD5108AFTA-5, EDD5116AFTA-5
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is
Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered
when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or
write access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
DM, LDM and UDM (input pins)
DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and
VREF. DMs provide the byte mask function. When DM = High, the data input at the same timing are masked while
the internal burst counter will be count up. In
×16
products, LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input/output pins)
Data is input to and output from these pins (DQ0 to DQ7; EDD5108AFTA, DQ0 to DQ15; EDD5116AFTA).
DQS, LDQS and UDQS (input and output pins)
DQS provides the read data strobes (as output) and the write data strobes (as input). In
×16
products, LDQS is the
lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0741E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
