EDE1104ACBG, EDE1108ACBG, EDE1116ACBG
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2-800, 667]
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
-6E
Speed bin
DDR2-800 (5-5-5)
DDR2-667 (5-5-5)
Parameter
Symbol
tRCD
tRP
min.
12.5
12.5
57.5
−400
max.
min.
15
max.
Unit
ns
Notes
Active to read or write command delay
Precharge command period
15
ns
Active to active/auto-refresh command time tRC
60
ns
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tAC
+400
+350
0.52
0.52
−450
−400
0.48
0.48
+450
+400
0.52
0.52
ps
10
10
tDQSCK −350
tCH (avg) 0.48
tCL(avg) 0.48
ps
tCK (avg) 13
tCK (avg) 13
CK low-level width
Min. (tCL(abs),
tCH(abs))
Min.(tCL(abs),
tCH(abs))
CK half period
tHP
ps
ps
6, 13
Clock cycle time
(CL = 6)
tCK (avg) 2500
8000
3000
8000
13
(CL = 5)
tCK (avg) 2500
tCK (avg) 3750
tCK (avg) 5000
tDH (base) 125
tDS (base) 50
8000
8000
8000
3000
3750
5000
175
8000
8000
8000
ps
ps
ps
ps
ps
13
13
13
5
(CL = 4)
(CL = 3)
DQ and DM input hold time
DQ and DM input setup time
100
4
Control and Address input pulse width for
each input
tIPW
0.6
0.6
tCK (avg)
tCK (avg)
DQ and DM input pulse width for each input tDIPW
0.35
0.35
Data-out high-impedance time from CK,/CK tHZ
DQS, /DQS low-impedance time from
CK,/CK
tAC max.
tAC max. ps
tAC max. ps
tAC max. ps
10
10
10
tLZ (DQS) tAC min.
tAC max. tAC min.
DQ low-impedance time from CK,/CK
tLZ (DQ) 2 × tAC min. tAC max. 2 × tAC min.
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
200
300
240
340
ps
DQ hold skew factor
tQHS
tQH
ps
ps
7
8
DQ/DQS output hold time from DQS
tHP – tQHS
tHP – tQHS
DQS latching rising transitions to associated
clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
tCK (avg)
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
0.35
0.35
0.2
0.2
2
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
nCK
tDSH
tMRD
tWPST
tWPRE
0.4
0.35
0.6
0.4
0.35
275
200
0.9
0.4
45
0.6
tCK (avg)
tCK (avg)
ps
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
tIH (base) 250
tIS (base) 175
5
4
ps
tRPRE
tRPST
tRAS
0.9
0.4
45
1.1
1.1
tCK (avg) 11
tCK (avg) 12
ns
Read postamble
0.6
0.6
Active to precharge command
70000
70000
Data Sheet E1173E40 (Ver. 4.0)
14
ELPIDA [ ELPIDA MEMORY ]
