EDE1104ACBG, EDE1108ACBG, EDE1116ACBG
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
Parameter
CL (IDD)
tRCD (IDD)
tRC (IDD)
tRRD (IDD)-
×4/×8
tRRD (IDD)-×16
tFAW (IDD)-
×4/×8
tFAW (IDD)-×16
tCK (IDD)
tRAS (min.)(IDD)
tRAS (max.)(IDD)
tRP (IDD)
tRFC (IDD)
5-5-5
5
12.5
57.5
7.5
10
35
45
2.5
45
70000
12.5
127.5
DDR2-667
5-5-5
5
15
60
7.5
10
37.5
50
3
45
70000
15
127.5
DDR2-533
4-4-4
4
15
60
7.5
10
37.5
50
3.75
45
70000
15
127.5
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDD7 Timing Patterns for 8 Banks
The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.
[×4/×8 organization]
Speed bins
DDR2-533
DDR2-667
DDR2-800
Timing Patterns
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
[×16 organization]
Speed bins
DDR2-533
DDR2-667
DDR2-800
Timing Patterns
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
Remark: A = Active. RA = Read with auto precharge. D = Deselect
Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using
a Burst length = 4.
2. Control and address bus inputs are STABLE during DESELECTs.
3. IOUT = 0mA.
Data Sheet E1173E40 (Ver. 4.0)
10
ELPIDA [ ELPIDA MEMORY ]
