EDJ1104BASE, EDJ1108BASE, EDJ1116BASE
Pin Configurations (×16 configuration)
/xxx indicates active low signal.
96-ball FBGA
1
2
3
7
8
9
A
VDDQ
DQU5 DQU7
DQU4
VDDQ
VSS
B
VSSQ
VDD
VSS
/DQSU
DQU6 VSSQ
DQSU
DQU2
VDDQ
DQU0
VSSQ
DML
VDD
C
VDDQ
DQU3
DQU1
D
E
VSSQ VDDQ
DMU
VSS
VSSQ
DQL0
VSSQ
VDDQ
F
VDDQ
DQL2
DQSL
DQL1
DQL3
VSSQ
VDD
VSS
VSSQ
G
VSSQ DQL6
/DQSL
H
VREFDQ VDDQ
DQL4
DQL7 DQL5 VDDQ
CK
VSS
NC
CKE
J
NC
VSS
VDD
/CS
/RAS
K
ODT
/CAS
/WE
/CK
A10(AP)
VDD
ZQ
L
NC
NC
M
VSS
BA0
A3
A5
A7
BA2
A0
A2
A9
NC
VREFCA
VSS
VDD
N
VDD
A12(/BC)
BA1
A1
A11
P
VSS
R
VDD
A4
A6
VSS
VDD
VSS
T
VSS
/RESET
NC
NC
A8
(Top view)
Pin name
A0 to A12*
2
Function
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
Bank select
Data input/output
Differential data strobe
Chip select
2
Pin name
/RESET*
VDD
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*
2
Function
Active low asynchronous reset
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
Reference pin for ZQ calibration
No connection
BA0 to BA2
DQU0 to DQU7
DQL0 to DQL7
DQSU, /DQSU
DQSL, /DQSL
/CS*
2
/RAS, /CAS, /WE*
CKE*
2
Command input
Clock enable
Differential clock input
Write data mask
ODT control
CK, /CK
DMU, DML
ODT*
2
Note: 1. Not internally connected with die.
2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1128E60 (Ver. 6.0)
4
ELPIDA [ ELPIDA MEMORY ]
