EDS1232AATA
Relationship Between Frequency and Minimum Latency
Parameter
Frequency (MHz)
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
lSEC
-60
166
6
3
10
7
3
2
2
1
5
10
⎯
3
1
⎯
–2
1
133
7.5
2
8
6
2
2
2
1
4
8
2
3
1
–1
–2
1
-75
133
7.5
3
9
6
3
2
2
1
5
9
⎯
3
1
⎯
–2
1
100
10
2
7
5
2
2
2
1
4
7
2
3
1
–1
–2
1
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Notes
1
1
1
1
1
1
2
= [lDPL +
lRP]
= [lRC]
3
EO
(CL = 3)
(CL = 3)
DQM to data in
DQM to data out
CKE to CLK disable
/CS to command disable
Data Sheet E0386E60 (Ver. 6.0)
Precharge command to high impedance
lHZP
(CL = 2)
lHZP
lAPR
lEP
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge
(early precharge)
(CL = 2)
Column command to column command
Write command to data in latency
Register set to active command
Power down exit to command input
Notes: 1.
lRCD
to
lRRD
are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
L
lEP
od
Pr
lCCD
lWCD
lDID
0
0
0
0
0
0
0
0
lDOD
lCLE
2
2
2
2
1
1
1
1
lMRD
lCDD
lPEC
2
2
2
2
0
0
0
0
1
1
1
1
t
uc
8