EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 2 (OD4): Open-Drain Control bit
0 = Open-drain disable for SCK
1 = Open-drain enable for SCK
Bit 1 are not used and read as “0”.
Bit 0 (RBF): Read Buffer Full flag
0 = Receiving not completed, and SPIRB has not fully exchanged. When
users read SPIRB, RBF bit will be cleared.
1 = Receiving completed; SPIRB is fully exchanged.
6.1.11 RD (SPIC: SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Bit 7 (CES): Clock Edge Select bit
0 = Data shifts out on a rising edge, and shifts in on a falling edge. Data is
on hold during a low-level.
1 = Data shifts out on a falling edge, and shifts in on a rising edge. Data is
on hold during a high-level.
Bit 6 (SPIE): SPI Enable bit
0 = Disable SPI mode
1 = Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0 = No overflow
1 = A new data is received while the previous data is still being held in the
SPIB register. In this situation, the data in SPIS register will be
destroyed. To avoid setting this bit, users are required to read the
SPIRB register although only the transmission is implemented.
NOTE
This can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0 = Reset as soon as the shifting is completed, and the next byte is ready
to shift.
1 = Start to shift, and remain on “1” while the current byte is still being
transmitted.
NOTE
This bit will reset to 0 at every one-byte transmission by the hardware
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
