EM78P447N
OTP ROM
Aaddress
R PAGE registers
IOC PAGE registers
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
︰
1F
20
：
3E
R0
R1
R2
R3
R4
R5
R6
R7
(Indirect Addressing Register)
(Time Clock Counter)
(Program Counter)
(Status Register)
(RAM Select Register)
(Port5)
(Port6)
(Port7)
General Register
General Register
General Register
General Register
General Register
General Register
General Register
General Register
IOCE
IOCF
IOCB
IOC5
IOC6
IOC7
Reserve
CONT
(Control Register)
Reserve
Reserve
Reserve
(I/O Port Control Register)
(I/O Port Control Register)
(I/O Port Control Register)
Reserve
Reserve
Reserve
(Wake-Up Control Register for Port6 )
Reverse
Reverse
(WDT,SLEEP2,Open Drain,R -Option
Control Register)
(Interrupt Mask Register)
General Registers
Bank0
Bank1
Bank2
Bank3
3F
R3F
(Interrupt Status Register)
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
10
10.21.2004 (V1.0)
EMC [ ELAN MICROELECTRONICS CORP ]
