EM78P447N
OTP ROM
4. FUNCTION DESCRIPTION
OSCI
OSCO
/R E S E T
TCC
/IN T
W D T T im e r
O s c illa to r/T im in g
C o n tro l
P C
STACK 1
STACK 2
STACK 3
P re s c a le
r
W DT
T im - o u t
e
ROM
In te rru p t
C o n tro l
STACK 4
STACK 5
R 1 (T C C )
In s tru c tio n
R e g is te r
ALU
S le e p
&
W ake
C o n tro l
RAM
In s tru c tio n
D ecoder
R3
R4
ACC
DATA & CO NTRO L BUS
IO C 5
R5
IO C 6
R6
IO C 7
R7
PPPPPPPP
55555555
0 1 2 3 45 6 7
PPPPPPPP
66666666
0 1 2 3 45 6 7
PPPPPPPP
77777777
0 1 2 3 45 6 7
Fig. 2 Functional Block Diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to act as an indirect addressing pointer.
Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB (CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
This specification is subject to change without prior notice.
8
10.21.2004 (V1.0)
EMC [ ELAN MICROELECTRONICS CORP ]
