merging Memory & Logic Solutions Inc.
AC OPERATING CONDITIONS
Test Conditions (Test
Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
CL = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
1)
EM611FV16U Series
Low Power, 64Kx16 SRAM
V
TM 3)
R
12)
CL
1)
R
22)
READ CYCLE
(V
cc
=2.7 to 3.6V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB acess time
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Symbol
t
RC
t
AA
t
co
t
O E
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
55ns
Min
55
-
-
-
Max
-
55
55
25
30
10
5
5
0
0
0
10
-
-
-
20
20
20
-
10
5
5
0
0
0
10
Min
70
-
-
-
70ns
Max
-
70
70
35
35
-
-
-
25
25
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(V
cc
=2.7 to 3.6V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Write cycle time
Chip select to end of write
Address setup time
Address valid to end of write
UB, LB valid to end of write
Write pulse width
Write recovery time
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
t
WC
t
CW
t
As
t
AW
t
BW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55ns
Min
55
45
0
45
45
40
0
0
25
0
5
-
-
Max
-
-
-
-
-
-
-
25
Min
70
60
0
60
60
50
0
0
30
0
5
70ns
Max
-
-
-
-
-
-
-
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
