merging Memory & Logic Solutions Inc.
EM611FV16U Series
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
t
WC
Address
t
CW
(2)
CS
t
A W
t
B W
UB ,LB
t
A S
(3)
WE
t
DW
Data in
Data out
High-Z
Data Valid
t
W R
(4)
t
W P
(1)
t
DH
High-Z
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The t
WP
is
measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
A S
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as CS
or WE going high.
8
EMLSI [ Emerging Memory & Logic Solutions Inc ]
