EM640FP16 Series
Low Power, 256Kx16 SRAM
3)
V
TM
AC OPERATING CONDITIONS
Test Load and Test Input/Output Reference)
Test Conditions (
2)
2)
R
R
1
2
Input Pulse Level : 0.2 to VCC-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 0.9V
Output Load (See right) : CL = 100pF+ 1 TTL
1)
1)
CL
CL = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R =3070 ohm
R =3150 ohm
2
,
1
3. V =1.8V
TM
o
o
READ CYCLE (V =1.65 to 2.2V, Gnd = 0V, T = -40 C to +85 C)
cc
A
70ns
Symbol
Parameter
Unit
Min
Max
Read Cycle Time
t
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address Access Time
t
-
-
-
70
70
35
70
-
AA
Chip Select to output
t
t
co1, co2
Output Enable to valid output
UB, LB Acess time
t
OE
t
BA
Chip select to low-Z output
UB, LB enable to low-Z output
Output Enable to Low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
t
t
10
10
5
LZ1, LZ2
t
-
BLZ
OLZ
t
-
t
t
0
25
25
25
-
HZ1, HZ2
t
0
BHZ
OHZ
t
0
t
OH
10
o
o
(V =1.65 to 2.2V, Gnd = 0V, T = -40 C to +85 C)
WRITE CYCLE
cc
A
70ns
Unit
Symbol
Parameter
Min
Max
Write Cycle Time
t
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Chip Select to end of write
Address Setup time
t
t
60
0
-
-
CW1, CW2
t
As
Address valid to end of write
UB, LB valid to end of write
Write pulse width
t
t
t
t
60
60
55
0
-
AW
BW
WP
WR
-
-
Write recovery time
-
Write to ouput high-Z
t
0
25
WHZ
Data to write time overlap
Data hold from write time
End write to output low-Z
t
30
0
DW
t
-
-
DH
t
5
OW
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
