EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING DIAGRAMS
(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL
)
TIMING WAVEFORM OF READ CYCLE(1).
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
(WE = V )
TIMING WAVEFORM OF READ CYCLE(2)
IH
t
RC
Address
t
AA
t
OH
t
CO
CS1
CS2
t
HZ
t
t
BA
OE
UB,LB
t
t
BHZ
OHZ
OE
t
OLZ
High-Z
Data Out
Data Valid
t
t
BLZ
WHZ
t
LZ
NOTES (READ CYCLE)
1. t and t
are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
HZ
OHZ
2. At any given temperature and voltage condition, t (Max.) is less than t (Min.) both for a given device and from device to device
HZ
LZ
interconnection.
6