EM6603
Debounced
PA0
is connected to CPU
TestVar1
Debounced
PA1
is connected to CPU
TestVar2
Debounced
PA2
is connected to CPU
TestVar3
Figure 6.Port A
Additionally, PA3 can also be used as the input terminal for the event counter (see section 8).
The input port PA(0:3) also has individually selectable interrupts. Each port has its own interrupt mask bit in the
MPortA
register. When an interrupt occurs inspection of the
IRQpA
and the
IntRq
registers allows the source
of the interrupt to be identified. The
IRQpA
register is automatically cleared by a RESET, by reading the
register. Reading
IRQpA
register also clears the
INTPA
flag in
IntRq
register. At initial RESET the
MPortA
is
set to 0, thus disabling any input interrupts.
See also section 9 for further details about the interrupt controller.
6.2
PortA registers
Bit
3
2
1
0
Name
PA3
PA2
PA1
PA0
Reset
-
-
-
-
R/W
R
R
R
R
Description
PA3 input status
PA2 input status
PA1 input status
PA0 input status
Table 11.PortA input status register - PortA
Table 12.PortA Interrupt request register - IRQpA
Bit
3
2
1
0
Name
IRQpa3
IRQpa2
IRQpa1
IRQpa0
Reset
0
0
0
0
R/W
R
R
R
R
Description
input PA3 interrupt request flag
input PA2 interrupt request flag
input PA1 interrupt request flag
input PA0 interrupt request flag
Table 13.PortA interrupt mask register - MportA
Bit
3
2
1
0
Name
MPA3
MPA2
MPA1
MPA0
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
interrupt mask for input PA3
interrupt mask for input PA2
interrupt mask for input PA1
interrupt mask for input PA0
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
10
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
