EM6603
3
Reset
To initialize the EM6603, a system RESET must be executed. There are four methods of doing this:
(1)
(2)
(3)
(4)
Initial RESET from the oscillation detection circuit.
External RESET from the RESET PIN.
External RESET by simultaneous high input to terminals PA0..PA3.
(Combinations defined by metal option)
Watchdog RESET (software option).
During any of these RESET’s the STB/RST output pin is high.
Figure 5.System reset generation
3.1
Oscillation detection circuit
At power on, the built-in voltage regulator starts to follow the supply voltage until Vdd becomes higher than Vreg.
Since it is Vreg which supplies the oscillator and this needs time to stabilise, Power-On-Reset with the oscillation
detection circuit therefore counts the first 32768 oscillator clocks after power-on and holds the system in RESET.
The system will consequently remain in RESET for at least one second after power up.
After power up the Analogue Watchdog circuit monitors the oscillator. If it stops for any reason other then SLEEP
mode, then a RESET is generated and the STB/RST pin is driven high.
3.2
Reset Pin
During active or STANDBY mode the RESET terminal has a debouncer to reject noise and therefore must be
active high for at least 2ms or 16ms (CLK = 32kHz) - software selectable by
DebCK
in
CIRQD
register. (see
Table 31)
At power on, or when cancelling SLEEP mode, the debouncer is not active and so RESET must satisfy the filter
time constant (typ. 1µsec) such that the RESET must be active high for at least 2µsec.
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
6
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
