R
H6006
Monitoring of the unregulated voltage require versions B1,
A2 and B2. The versions are based on the principle that V
DD
rises with V
IN
on power-up and V
DD
holds up for a certain
time after V
IN
starts dropping on power-down. The version B1
has a 100 k
Ω
nominal resistance from V
IN
to V
SS
(internal
voltage divider). The versions A2, B2, A3 and B3 have high
impedance V
IN
inputs (see Fig. 7 and Table 4) for external
threshold voltage programming by a voltage divider on pin
V
IN.
The levels obtained are proportional to the internal levels
V
SH
, V
SL
and V
RL
on the chip itself (see Electrical
Specifications).
Timer Clearing and
RES
Action
A negative edge or a negative pulse at the TCL input
longer than 150 ns will reset the timer and set TO high. If
a further TCL signal edge or pulse is applied before T
TO
timeout, TO will stay high and the timer will again be reset
to zero (see Fig. 5). If no TCL signal is applied before the
T
TO
timeout, TO will start to generate a square wave of
period 2 x T
TO
starting with a low state. If no TCL signal is
applied during the first low state of TO , then the RES
output will go low and stay low until the next TCL signal,
or until a fresh power-up sequence.
Combined Voltage and Timer Action
The combination of voltage and timer action is illustrated by
the sequence of events shown in Fig. 6. One timeout period
after V
IN
reached V
SH
, during power-up, RES goes inactive
high. No TCL pulse will have any effect until this power-on
reset delay is completed. After completing the power-up
sequence the watchdog timer starts acting. If no TCL pulse
occurs, the timeout warning TO goes active low after one
timeout period T
TO
. After each subsequent timeout period
without a timer clear pulse TCL , TO changes its polarity
providing a square wave signal. RES activates at the end
of the first low state of the TO signal. A TCL pulse clears
the watchdog timer and resets the TO and RES output
inactive high again. A voltage drop below the V
RL
level
overrides the timer and immediately forces RES and
SAVE active low and disables TO . Any further TCL pulse
has no effect until the next power-up sequence has
complete
Timer Programming
With pin RC unconnected, the on-chip RC oscillator together
with its divider chain give a timeout T
TO
of typically 10 ms.
For programming a different T
TO
, an approximation for
calculating component values is given by the formula:
⎡
⎤
⎢
(32
+
C
1
)
•
1.6
⎥
=⎢
0.75
+
⎥ •
1.024
V
DD
−
0.8
⎥
⎢
5.5
+
⎢
⎥
R
1
⎣
⎦
T
TO
R
1
min. = 10 kΩ, C
1 max
. = 1
µF
If R
1
is in MΩ and C
1
in pF, T
TO
will be in ms.
Thus, a resistor decreases and a capacitor increases the
interval to timeout. By using both external components,
excellent temperature stability of T
TO
can be achieved. With
TCL tied to either V
DD
or V
SS,
a precise square wave of
period 2 x T
TO
is generated at the output TO . The oscillator
and watchdog timer run so long as the chip is powered with
at least the minimum positive supply voltage specified (V
ON
),
and so long as V
IN
remains above the level V
RL
after a
power-up sequence. If the timer function is not required,
input TCL should be tied to output TO to give a simple
voltage monitor (see Fig. 14).
Typical Applications
>9 V
R
1
= 470 kΩ
Monitored
Voltage
Voltage
Regulator
V
IN
V
DD
5V
Adress
Decoder
SEL
Latched
Address Bus
RD
Microprocessor
H6006
TCL
RC
C
1
=
220 pF
RESET
IR 1
IR 2
V
SS
TO
SAVE
RES
CS Disable
RAM
T
TO
=~ 30 ms
Fig. 11
Copyright © 2004, EM Microelectronic-Marin SA
6
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