R
V6108
cascading devices the STR lines should all be
connected.
Functional Description
Supply voltages VLCD, VDD , VSS
VDD is the positive supply line for the logic and VLCD for
the display signals. VLCD has to be equal or higher than
R Input
When R is active (high), the display is blanked: all
segment outputs are tied VSS.. R does not clear the
information in the latches.
VDD . All voltages are specified relative VSS.
Data Input / Output (DI / DO)
The data input pin (DI) accepts serial data from the data
source. The data is clocked in a rate determined by the
Segment Driver
The number of segment drivers available on the chip is
40. Each segment driver can be used as backplane-
driver. If two or more drivers are connected together,
care must be taken to ensure the drivers do not cause
circuit malfunction by driving one against the other.
clock input frequency (CLK).
A logic “1” on DI
corresponds to a visible segment when the backplane is
driven by a signal corresponding to logic “0”. The data at
DO is equal to the data at DI delayed by 40 clock
periods. In order to cascade devices the DO of one chip
must be connected to DI of the following chip (see Fig.1).
FR Input
This input controls the segment output switching
frequency according to Table 6. It must be connected to
an external clock signal. When cascading devices, their
FR inputs may all be connected to a common signal.
CLK Input
The clock input pin (CLK) is used to clock the DI serial
data into the 40-bit shift register. Loading, shifting and
outputting of the data occurs at the falling edge of this
clock (see Fig.3). When cascading devices , all CLK lines
should be tied together.
Segment Switching Table
Latched Signal (DI)
Signal Segment Voltage
0= VIL 1= VIH
FR
0= Vss 1= VLCD
STR Input
The strobe input pin (STR) is used to latch the input data
shifted into the 40-bit shift register. The latched data is
held for display. A logic “1” on the STR input transfers
the data contained in the shift register cells to the
corresponding latches. The latches remain open during
the whole time STR remains at logic “1”. When
0
0
1
1
0
1
0
1
0
1
1
0
Table 6
Typical Applications
Type V6108 Circuits Driving a 79 Segment Display
Fig.9
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6
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