EN25LF40
Manufacturer/
Device ID
Read Identification
Enter OTP mode
90h
9Fh
3Ah
dummy
(M7-M0)
dummy
(ID15-ID8)
00h
01h
(ID7-ID0)
(M7-M0)
(ID7-ID0)
(5)
(ID7-ID0)
(M7-M0)
(4)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin.
2. The Status Register contents will repeat continuously until CS# terminate the instruction.
3. The Device ID will repeat continuously until CS# terminate the instruction.
4. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
5. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity
Table 5. Manufacturer and Device Identification
OP Code
ABh
90h
9Fh
1Ch
1Ch
3113h
(M7-M0)
(ID15-ID0)
(ID7-ID0)
12h
12h
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase
(BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
Figure 5. Write Enable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
10
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. G, Issue Date: 2010/05/31
EON [ EON SILICON SOLUTION INC. ]
