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EN25LF40_1 参数 Datasheet PDF下载

EN25LF40_1图片预览
型号: EN25LF40_1
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位串行闪存与4KB的扇区制服 [4 Megabit Serial Flash Memory with 4Kbytes Uniform Sector]
分类和应用: 闪存
文件页数/大小: 35 页 / 1378 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25LF40
Table 3. Protected Area Sizes Sector Organization
Status Register
Content
BP2
BP1
BP0
Bit
Bit
Bit
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Memory Content
Protect Areas
None
Sector 0 to 125
Sector 0 to 123
Sector 0 to 119
Sector 0 to 111
Sector 0 to 95
Sector 0 to 63
All
Addresses
None
000000h-07DFFFh
000000h-07BFFFh
000000h-077FFFh
000000h-06FFFFh
000000h-05FFFFh
000000h-03FFFFh
000000h-07FFFFh
Density(KB)
None
504KB
496KB
480KB
448KB
384KB
256KB
512KB
Portion
None
Lower 126/128
Lower 124/128
Lower 120/128
Lower 112/128
Lower 96/128
Lower 64/128
All
Hold Function
The Hold (HOLD#) signal is used to pause any serial communications with the device without resetting
the clocking sequence. However, taking this signal Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold
condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial
Clock (CLK) being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with
Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after
Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)
being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment
of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting
the internal logic of the device. To restart communication with the device, it is necessary to drive Hold
(HOLD#) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to
the Hold condition.
Figure 4. Hold Condition Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. G, Issue Date: 2010/05/31