EM48BM0884VTA
256Mb (8M×4Bank×8) Synchronous DRAM
Features
Description
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
The EM48BM0884VTA is Synchronous Dynamic
Random Access Memory (SDRAM) organized
as 8Meg words x 4 banks by 8 bits. All inputs
and outputs are synchronized with the positive
edge of the clock.
• Programmable CAS Latency (C/L) - 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
The 256Mb SDRAM uses synchronized
pipelined architecture to achieve high speed
data transfer rates and is designed to operate at
3.3V low power memory system. It also provides
auto refresh with power saving / down mode. All
inputs and outputs voltage levels are compatible
with LVTTL.
• Burst Read with Single-bit Write Operation
• All Inputs are sampled at the Rising Edge of
the System Clock
Available packages: TSOPII 54P 400mil.
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM48BM0884VTA-6F
32M X 8
166MHz @CL3
54pin TSOP(ll) Commercial
Free
EM48BM0884VTA-7F
32M X 8
143MHz @CL3
54pin TSOP(ll) Commercial
Free
Aug. 2011
2/20
www.eorex.com
EOREX [ EOREX CORPORATION ]
