PBM 3960/1
Electrical Characteristics
Electrical characteristics over recommended operating conditions.
Ref.
Parameter
Symbol fig Conditions
Min
Typ
Max
Unit
Logic Inputs
Reset logic HIGH input voltage VIHR
Reset logic LOW input voltage VILR
3.5
2.0
V
V
V
V
mA
µA
pF
0.1
Logic HIGH input voltage
Logic LOW input voltage
Reset input current
VIH
VIL
IIR
II
0.8
1
1
VSS < VIR < VDD
VSS < VI < VDD
-0.01
-1
Input current, other inputs
Input capacitance
3
Internal Timing Characteristics
Address setup time
Data setup time
Chip select setup time
Address hold time
Data hold time
Chip select hold time
Write cycle length
tas
tds
tcs
tah
tdh
tch
tWR
tR
2
2
2
2
2
2
2
3
Valid for A0, A1
Valid for D0 - D7
60
60
70
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
50
80
Reset cycle lenght
Reference Input
Input resistance
RRef
6
9
kΩ
Logic Outputs
Logic HIGH output current
Logic LOW output current
Write propagation delay
IOH
IOL
tpWR
VO = 2.4 V
VO = 0.4 V
From positive edge of WR.
outputs valid, Cload = 120 pF
From positive edge of Reset to
outputs valid, Cload = 120 pF
-13
5
30
-5
mA
mA
ns
1.7
2
3
100
150
Reset propagation delay
tpR
60
ns
DAC Outputs
Nominal output voltage
Resolution
Reset open, VRef = 2.5 V
VDA
0
VRef- 1LSB V
Bits
7
Offset error
Gain error
Endpoint nonlinearity
Differential nonlinearity
Load error
7
7
7
5, 6
0.2
0.1
0.2
0.2
0.1
0.5
0.5
0.5
0.5
0.5
LSB
LSB
LSB
LSB
LSB
(VDA, unloaded - VDA, loaded)
Rload = 2.5 kΩ, Code 127 to DAC
Power supply sensitivity
Conversion speed
Code 127 to DAC
4.75 V < VDD < 5.25 V
For a full-scale transition to ±0.5 LSB
0.1
3
0.3
8
LSB
tDAC
2
µs
of final value, Rload = 2.5 kohm, Cload = 50 pF.
3