PBM 3960/1
V
1
2
3
4
5
6
7
8
9
22 Reset
ref
DA
Sign
CD
21
20
19
18
DA
1
1
2
Sign
2
5
6
7
8
9
25
24
23
22
21
20
19
N/C
D0
D1
D2
N/C
D3
D4
D5
CD
2
1
DA
2
V
V
DD
SS
PBM
3960/1N
Reset
PBM
3960/1QN
WR
17 CS
N/C
V
16
D7
D6
D5
A1
ref
DA 10
1
15 A0
14 D0
11
N/C
D4 10
D3 11
13
12
D1
D2
Figure 4. Pin configuration.
Pin Descriptions
Refer to figure 4.
DIP
PLCC
Symbol
Description
1
2
3
9
10
12
VRef
DA1
Sign1
Voltage reference supply pin, 2.5 V nominal (3.0 V maximum)
Digital-to-Analog 1, voltage output. Output between 0.0 V and VR - 1 LSB.
Sign 1, TTL/CMOS level. To be connected directly to PBL 3771 Phase input.
Databit D7 is transfered non inverted from PBM 3960/1/1 data input.
Current Decay 1, TTL/CMOS level. The signal is automatically generated when
decay level is programmed. LOW level = fast current decay.
Voltage Drain-Drain, logic supply voltage. Normally +5 V.
Write, TTL/CMOS level, input for writing to internal registers.
Data is clocked into flip flops on positive edge.
4
13
CD1
5
6
14
15
VDD
WR
7
8
9
10
11
12
13
14
15
16
17
19
20
21
23
24
25
27
D7
D6
D5
D4
D3
D2
D1
D0
A0
Data 7, TTL/CMOS level, input to set data bit 7 in data word.
Data 6, TTL/CMOS level, input to set data bit 6 in data word.
Data 5, TTL/CMOS level, input to set data bit 5 in data word.
Data 4, TTL/CMOS level, input to set data bit 4 in data word.
Data 3, TTL/CMOS level, input to set data bit 3 in data word.
Data 2, TTL/CMOS level, input to set data bit 2 in data word.
Data 1, TTL/CMOS level, input to set data bit 1 in data word.
Data 0, TTL/CMOS level, input to set data bit 0 in data word.
Address 0, TTL/CMOS level, input to select data transfer,
A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH).
Address 1, TTL/CMOS level, input to select data transfer. A1 selects between normal
D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH).
Chip Select, TTL/CMOS level, input to select chip and activate data transfer
from data inputs. LOW level = chip is selected.
16
17
18
19
20
28
1
A1
CS
2
VSS
Voltage Source-Source. Ground pin, 0 V reference for all signals and
measurements unless otherwise noted.
3
CD2
Sign2
Current Decay 2, TTL/CMOS level. The signal is automatically generated
when decay level is programmed. LOW level = fast current decay .
Sign 2. TTL/CMOS level. To be connected directly to PBL 3771 sign input.
Data bit D7 is transfered non-inverted from PBM 3960/1 data input.
Digital-to-Analog 2, voltage output. Output between 0.0 V and Vref - 1 LSB.
Reset, digital input resetting internal registers.
4
21
22
6
7
DA2
Reset
HIGH level = Reset, VRes ≥ 3.5 V = HIGH level. Pulled low internally.
Not Connected
5
8
Not Connected
11
18
22
26
Not Connected
Not Connected
Not Connected
Not Connected
4
ERICSSON [ ERICSSON ]
