ESMT
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L004A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, or Chip-Erase
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE . Inputs will be accepted on the rising edge of
F25L004A
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Cycle Type/
1,2
Operation
Read
High-Speed-Read
Sector-Erase
4,5
(4K Byte)
Block-Erase
5
(64K Byte)
Chip-Erase
5
Byte-Program
5
Auto-Address-Increment-word
programming (AAI)
6
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)
8
Write-Status-Register
(WRSR)
8
Write-Enable (WREN)
11
Write-Disable (WRDI)
Read-Electronic-Signature
(RES)
9
S
IN
S
OUT
33
MHz
03H Hi-Z
0BH Hi-Z
20H Hi-Z
D8H Hi-Z
60H
Hi-Z
C7H
02H Hi-Z
Max
Freq
1
2
S
IN
A
23
-A
16
A
23
-A
16
A
23
-A
16
A
23
-A
16
-
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
Bus Cycle
3
4
5
6
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z X D
OUT
A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z X
X
X D
OUT
A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
-
-
-
-
A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
-
-
-
-
-
-
-
-
-
D
IN
-
Hi-Z
-
-
-
-
A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
ADH Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z D
IN
0 Hi-Z D
IN
1 Hi-Z
05H
50
MHz
50H
01H
06H
04H
100
MHz
ABH
9FH
90H
(A0=0)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
-
Data
-
-
X
X
D
OUT
-
Hi-Z
-
-
12H
8CH
-
-
-
-
-
-
X
Note
7
-
-
-
-
-
20H
-
-
-.
-
-
-
X
Note
7
-
-
-
-
-
13H
-
-
-
-
-
-
-
X
-
-
Note
7
-
-
-
-
-
-
8CH
12H
-
-
-
-
-
-
-
-
-
X
-
-
-
-
-
-
-
12H
8CH
Jedec-Read-ID (JEDEC-ID)
10
Read-ID (RDID)
Enable SO to output RY/BY#
Status during AAI (EBSY)
Disable SO to output RY/BY#
Status during AAI (DBSY)
1.
2.
3.
4.
5.
6.
7.
8.
90H
(A0=1)
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
70H
80H
Operation: S
IN
= Serial In, S
OUT
= Serial Out
X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
One bus cycle is eight clock periods.
Sector addresses: use AMS-A12, remaining addresses can be V
IL
or V
IH
Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
9.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.6
7/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
