ESMT
AC OPERATING TEST CONDITIONS
(VDD = 3.3V
±
0.3V
，TA
= -25 to 85
°
C )
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
VALUE
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
M12L64164A
Operation temperature condition -25℃ ~ 85℃
UNIT
V
V
ns
V
3.3V
1200
Ω
Output
870
Ω
50pF
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
Z0 =50
Ω
Vtt = 1.4V
50
Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
Row active to row active delay
SYMBOL
-6
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
@ Operating
Row cycle time
@ Auto refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
Output data
t
RC(min)
t
RFC(min)
t
CDL(min)
t
RDL(min)
t
BDL(min)
t
CCD(min)
CAS latency = 3
CAS latency = 2
58
60
1
2
1
1
2
1
12
18
18
40
100
63
70
VERSION
-7
14
20
20
42
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ea
1
1,5
2
2
2
3
4
1
1
1
1
UNIT
NOTE
RAS
to
CAS
delay
Row precharge time
Row active time
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2004
Revision: 0.1
5/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
