ESMT
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
M12L64164A
Operation temperature condition -25℃ ~ 85℃
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A13~A12
RFU
A11~A10/AP
RFU
A9
RFU
A8
TM
A7
A6
A5
A4
A3
BT
A2
A1
A0
CAS Latency
Burst Length
Test Mode
A8
0
0
1
1
A7
0
1
0
1
Type
Mode Register Set
Reserved
Reserved
Reserved
A6
0
0
0
0
1
1
1
1
CAS Latency
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
A3
0
1
Type
Sequential
Interleave
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
Burst Length
A0
0
1
0
1
0
1
0
1
BT = 0
1
2
4
8
BT = 1
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Full Page Length : 256
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note :
1. RFU(Reserved for future use) should stay “0” during MRS cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2004
Revision: 0.1
9/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
