ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (V
REF
)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (V
IH
/V
IL
)
Input timing measurement reference level
Output timing reference level
Value
0.5*V
DDQ
1.5
1.0
V
REF
+0.35/V
REF
-0.35
V
REF
V
TT
M13S128324A
Operation Temperature Condition -40~85°C
Unit
V
V
V/ns
V
V
V
AC Timing Parameter & Specifications
(V
DD
= 2.375V~2.75V, V
DDQ
=2.375V~2.75V, T
A
=-40 °C to 85 °C )(Note)
Parameter
CL2
CL2.5
Clock Period
CL3
CL4
Access time from CLK/ CLK
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each input)
Symbol
-5
Min
7.5
6.0
Max
12
12
12
12
+0.7
0.55
0.55
+0.7
1.2
-
-
-
-
-
-
0.6
0.6
-
-
0.45
+0.7
+0.7
Min
7.5
6.0
6.0
6.0
-0.7
0.45
0.45
-0.7
0.8
0.45
0.45
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
-6
Max
12
12
ns
12
12
+0.7
0.55
0.55
+0.7
1.2
-
-
-
-
-
-
0.6
0.6
-
-
0.45
+0.7
+0.7
ns
t
CK
t
CK
ns
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
ns
ns
ns
t
CK
5.0
5.0
t
AC
t
CH
t
CL
t
DQSCK
t
DQSS
t
DS
t
DH
t
DIPW
t
IS
t
IH
t
IPW
t
DQSH
t
DQSL
t
DSS
t
DSH
t
DQSQ
t
HZ
t
LZ
-0.7
0.45
0.45
-0.7
0.8
0.45
0.45
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Control and Address input pulse width
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/
CLK
Data-out low-impedance window from
CLK/ CLK
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
7/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
