ESMT
Pin Description
Pin Name
Function
Address inputs
- Row address A0~A12
- Column address A0~A9
A10/AP : Auto Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Command input
Command input
Command input
Ground
Power
Bi-directional differential Data Strobe.
LDQS and /LDQS are DQS for DQ0~DQ7;
UDQS and /UDQS are DQS for DQ8~DQ15.
On-Die-Termination.
ODT is only applied to DQ0~DQ15, DM, DQS
and /DQS.
No connection
Pin Name
M14D5121632A
Function
DM is an input mask signal for write data.
LDM is DM for DQ0~DQ7 and UDM is DM
for DQ8~DQ15.
Differential clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage
A0~A12,
BA0,BA1
DM
(LDM, UDM)
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
V
SS
V
DD
DQS,
(LDQS,
UDQS,
ODT
NC
)
V
DDL
Supply Voltage for DLL
V
SSDL
Ground for DLL
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDL
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit output current
Symbol
V
IN
, V
OUT
V
DD
V
DDL
V
DDQ
T
STG
P
D
I
OUT
Value
-0.5 ~ 2.3
-1.0 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
-55 ~ +100
1
50
Unit
V
V
V
V
°C (
Note *)
W
mA
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Note *:
Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
4/59
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
