ESMT
AC Test Loads and Waveforms
M24L416256SA
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics (Over the Operating Range)[10]
Prameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[11, 13]
OE HIGH to High Z[11, 13]
CE LOW to Low Z[11, 13]
CE HIGH to High Z[11, 13]
BLE / BHE LOW to Data Valid
BLE
/
BHE
LOW to Low Z[11, 13]
–55
Min.
55
55
5
55
25
5
25
2
25
55
5
10
0
55
45
45
0
0
40
60
45
45
0
0
40
5
2
5
8
Max.
Min.
60
–60
Max.
Min.
70
60
10
60
25
5
25
5
25
60
5
10
5
70
60
55
0
0
45
–70
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
35
25
25
70
25
10
t
HZBE
BLE
/
BHE
HIGH to High-Z[11, 13]
[14]
t
SK
Address Skew
Write Cycle[12]
t
WC
Write Cycle Time
t
SCE
CE LOW to Write End
t
AW
Address Set-up to Write End
t
HA
Address Hold from Write End
t
SA
Address Set-up to Write Start
t
PWE
WE
Pulse Width
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of V
CC(typ)
/2, input pulse levels of 0V to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test
Loads and Waveforms” section.
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
12. The internal Write time of the memory is defined by the overlap of
WE
, CE = V
IL
,
BHE
and/or
BLE
= V
IL
. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4
5/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
