M24L416256SA-70TIG 参数 Datasheet PDF下载

ESMT

Switching Waveforms (continued)

Write Cycle 1 (

WE

Controlled)[12, 13, 17, 18, 19]

M24L416256SA

Write Cycle 2 (

CE

Controlled)[12, 13, 17, 18, 19]

Notes:

17.Data I/O is high-impedance if OE

≥

V

IH

.

18.If Chip Enable goes INACTIVE with

WE

= V

IH

, the output remains in a high-impedance state.

19.During this period in the DATA I/O waveform, the I/Os could be in the output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2008

Revision: 1.4

7/14