ESMT
FUNCTIONAL BLOCK DIAGRAM
M52D32321A
Bank Select
Data Input Register
LWE
LDQM
512K x 32
512K x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
L(U)DQM
CS
RAS
CAS
WE
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10
BA
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
Data Output
Power/Ground
No Connection/
Reserved for Future Use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
DQM0~3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May 2009
Revision
:
1.6
2/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
