ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V, T
A
= 0 °C ~ 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
M52S64322A
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
@ Auto refresh
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh
Command
Refresh period(4K cycle)
Number of valid output
data
Symbol
-7.5
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
Row cycle time
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
MRD
(min)
t
REF
(max)
CAS latency=3
CAS latency=2
75
75
1
2
1
1
2
64
2
1
15
20
20
45
100
100
100
Version
-10
20
30
30
50
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
CLK
ms
ea
1
1
1
1
-
1
1,5
2
2
2
3
-
6
4
Unit
Note
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
5/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
