ST16C1450
2.97V TO 5.5V UART
xr
REV. 4.2.1
T
ABLE
1: T
YPICAL DATA RATES WITH A
14.7456 MH
Z CRYSTAL OR EXTERNAL CLOCK
O
UTPUT
Data Rate
400
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
D
IVISOR FOR
16x
Clock (Decimal)
2304
384
192
96
48
24
12
6
4
2
1
D
IVISOR FOR
16x
Clock (HEX)
900
180
C0
60
30
18
0C
06
04
02
01
DLM P
ROGRAM
V
ALUE
(HEX)
09
01
00
00
00
00
00
00
00
00
00
DLL P
ROGRAM
V
ALUE
(HEX)
00
80
C0
60
30
18
0C
06
04
02
01
D
ATA
R
ATE
E
RROR
(%)
0
0
0
0
0
0
0
0
0
0
0
2.4
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and an 8-bit Transmit Holding
Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods. The
transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and
adds the stop-bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit-5 and bit-
6).
2.4.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out.
2.4.2
Transmitter Operation
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. The THR flag can generate a transmit empty interrupt (ISR bit-1) when it is
enabled by IER bit-1. The TSR flag (LSR bit-6) is set when both the THR and TSR become completely empty.
6
EXAR [ EXAR CORPORATION ]
