xr
REV. 4.2.1
ST16C1450
2.97V TO 5.5V UART
F
IGURE
4. T
RANSMITTER
O
PERATION
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
Transmit Shift Register (TSR)
M
S
B
L
S
B
TXNOFIFO1
2.5
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and an 8-bit Receive Holding Register
(RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in
the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this
time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled
and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the
LSR register bits 2-4. Upon unloading the receive data byte from RHR, the error tags are immediately updated
to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon
receiving a character. The RHR interrupt is enabled by IER bit-0.
2.5.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. When there is data in the RHR register,
the 3 error tags in LSR register (bits 2-4) indicates if there are any errors associated with that byte.
7
EXAR [ EXAR CORPORATION ]
