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XRT73LC04AIV 参数 Datasheet PDF下载

XRT73LC04AIV图片预览
型号: XRT73LC04AIV
PDF下载: 下载PDF文件 查看货源
内容描述: 4路DS3 / E3 / STS - 1线路接口单元 [4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT]
分类和应用: 数字传输接口电信集成电路电信电路PC
文件页数/大小: 64 页 / 726 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT73LC04A  
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT  
REV. 1.0.1  
b. Operating in the Hardware Mode.  
put to the Receive Terminal Equipment via the RPOS,  
RNEG and RxClk output pins. Additionally, this data  
is also internally looped back into the Pulse-Shaping  
block within the Transmit Section. At this point, this  
data is routed through the remainder of the Transmit  
Section of the channel and transmitted out onto the  
line via the TTIP_(n) and TRing_(n) output pins.  
To configure Channel (n) to operate in the Digital Lo-  
cal Loop-Back Mode, pull both the LLB input pin and  
the RLB input pin "High".  
4.3 THE REMOTE LOOP-BACK MODE  
When a given channel is configured to operate in the  
Remote Loop-Back Mode, the channel ignores any  
signals that are input to the TPData and TNData input  
pins. The channel receives the incoming line signal  
via the RTIP and RRing input pins. This data is pro-  
cessed through the entire Receive Section and is out-  
Figure 35 illustrates the path that the data takes when  
the chip is configured to operate in the Remote Loop-  
Back Mode.  
FIGURE 35. THE REMOTE LOOP-BACK PATH, WITHIN A GIVEN CHANNEL  
RLOL_(n) EXClk_(n)  
RTIP_(n)  
AGC/  
Equalizer  
Clock  
Recovery  
Slicer  
Invert  
RxClk_(n)  
RRing_(n)  
REQEN_(n)  
Peak  
Detector  
Data  
Recovery  
RPOS_(n)  
RNEG_(n)  
LCV_(n)  
HDB3/  
B3ZS  
Decoder  
LOS Detector  
LOSTHR_(n)  
SDI  
RLOS_(n)  
LLB_(n)  
RLB_(n)  
SDO  
Serial  
Processor  
Interface  
Remote  
Loop-Back Path  
SClk  
Loop MUX  
CS/(SR/DR)  
REGR  
TAOS_(n)  
TPData_(n)  
TNData_(n)  
TxClk_(n)  
TTIP_(n)  
HDB3/  
B3ZS  
Encoder  
Transmit  
Logic  
Pulse  
Shaping  
Duty Cycle Adjust  
TRing_(n)  
TxLEV_(n)  
TxOFF_(n)  
DMO_(n)  
MTIP_(n)  
Device  
Monitor  
MRing_(n)  
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels  
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in  
Hardware Mode.  
Configure a channel to operate in the Remote Loop-  
Back Mode by employing either one of the following  
two steps  
COMMAND REGISTER CR4-(n)  
D4  
X
D3  
D2  
D1  
D0  
a. Operating in the HOST Mode  
STS-1/DS3_(n)  
X
E3_(n) LLB_(n) RLB_(n)  
To configure Channel (n) to operate in the Remote  
Loop-Back Mode, write a "1" into the RLB bit-field,  
and a "0" into the LLB bit-field, within Command Reg-  
ister CR4.  
X
X
0
1
b. Operating in the Hardware Mode  
To configure Channel(n) to operate in the Remote  
Loop-Back Mode, pull both the RLB_(n) input pin to  
“High" and the LLB_(n) input pin to "Low".  
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