XRT73LC04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
4.0 DIAGNOSTIC FEATURES OF THE
XRT73LC04A
The XRT73LC04A supports equipment diagnostic ac-
tivities by supporting the following Loop-Back modes
within each channel.
•
Analog Local Loop-Back.
•
Digital Local Loop-Back
•
Remote Loop-Back
N
OTE
:
In this data sheet we use the convention that Chan-
nel(n) refers to either channel 0, 1, 2 or 3. Similarly, specific
input and output pins uses this convention to denote which
channel it is associated with.
4.1 T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When a given channel is configured to operate in the
Analog Local Loop-Back Mode, the channel ignores
any signals that are input to its RTIP_(n) and
RRing_(n) input pins. The Transmitting Terminal
Equipment transmits clock and data into this channel
via the TPData_(n), TNData_(n) and TxClk_(n) input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder. Finally, this data is output to the line via the
TTIP_(n) and TRing_(n) output pins. Additionally, this
data which is being output via the TTIP_(n) and
TRing_(n) output pins is also looped back into the At-
tenuator/Receive Equalizer Block. Consequently, this
data is processed through the entire Receive Section
of the channel. After this post-Loop-Back data has
been processed through the Receive Section it out-
puts to the Near-End Receiving Terminal Equipment
via the RPOS_(n), RNEG_(n) and RxClk_(n) output
pins.
the channel is configured to operate in the Analog Lo-
cal Loop-Back Mode.
F
IGURE
33. A
CHANNEL OPERATING IN THE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
RLOL_(n) EXClk_(n)
RTIP_(n)
RRing_(n)
REQEN_(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
Data
Recovery
LOS Detector
Invert
RxClk_(n)
HDB3/
B3ZS
Decoder
RPOS_(n)
RNEG_(n)
LCV_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS/(SR/DR)
REGR
Serial
Processor
Interface
RLOS_(n)
Analog Local
Loop-Back Path
Loop MUX
LLB_(n)
RLB_(n)
TAOS_(n)
TTIP_(n)
Pulse
Shaping
TRing_(n)
TxLEV_(n)
TxOFF_(n)
DMO_(n)
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
TPData_(n)
TNData_(n)
TxClk_(n)
MTIP_(n)
MRing_(n)
Device
Monitor
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
Configure a given channel to operate in the Analog
Local Loop-Back Mode by employing either one of
the following two steps
a. Operating in the HOST Mode
N
OTE
:
See Table 2 for a description of Command Regis-
ters and Addresses for the different channels.
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a “1" into the LLB_(n) bit-
field and a "0" into the RLB_(n) bit-field within Com-
mand Register CR4.
47
EXAR [ EXAR CORPORATION ]
