XRT73LC04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
COMMAND REGISTER CR4-(n)
D4
X
X
D3
STS-1/DS3_(n)
X
D2
E3_(n)
X
D1
LLB_(n)
1
D0
RLB_(n)
0
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin (pin
76, 84, 97 or 105) “High" and the RLB_(n) input pin
(pin 77, 85, 96 or 104) "Low".
4.2 T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
.
When a given channel is configured to operate in the
Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT73LC04A via the TP-
Data, TNData and TxClk input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
PLL and the HDB3/B3ZS Encoder block. At this
point, this data is looped back to the HDB3/B3ZS De-
coder block. After this post-Loop-Back data has been
processed through the HDB3/B3ZS Decoder block, it
outputs to the Near-End Receiving Terminal Equip-
ment via the RPOS, RNEG and RxClk output pins.
the chip is configured to operate in the Digital Local
Loop-Back Mode.
F
IGURE
34. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK PATH WITHIN A GIVEN CHANNEL
RLOL_(n) EXClk_(n)
RTIP_(n)
RRing_(n)
REQEN_(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
RxClk_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS/(SR/DR)
REGR
Serial
Processor
Interface
LOS Detector
HDB3/
B3ZS
Decoder
RPOS_(n)
RNEG_(n)
LCV_(n)
Digital Local
Loop-Back Path
Loop MUX
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TTIP_(n)
Pulse
Shaping
TRing_(n)
TxLEV_(n)
TxOFF_(n)
DMO_(n)
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
TPData_(n)
TNData_(n)
TxClk_(n)
MTIP_(n)
MRing_(n)
Device
Monitor
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
Configure a channel to operate in the Digital Local
Loop-Back Mode by employing either one of the fol-
lowing two-steps:
a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, write a "1" into both the LLB
and RLB bit-fields within Command Register CR4-(n).
COMMAND REGISTER CR4-(n)
D4
X
X
D3
STS-1/DS3_(n)
X
D2
E3_(n)
X
D1
D0
LLB_(n) RLB_(n)
1
1
48
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