CMP1617BAx-E
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : C
L
=30pF+1TTL
30pf
CMOS LPRAM
1TTL
AC CHARACTERISTICS
(V
CC
=2.7V~3.3V, Extended product : T
A
=-25 to 85’C)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
/UB, /LB Access Time
Read
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High- Z Output
/UB, /LB Disable to High- Z Output
Output Disable to High- Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Page Mode Cycle Time
Page
Page Mode Address Access Time
Maximum Cycle Time
/CS High Pulse Width
tRC
tAA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tHZ
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
tPC
tPAA
tMRC
tCP
60
-
-
-
-
10
10
5
0
0
0
5
60
50
0
50
50
50
0
0
20
0
5
25
-
-
10
60ns
Max
40k
60
60
25
60
-
-
-
5
5
5
-
40k
-
-
-
-
-
-
5
-
-
-
-
25
40k
-
Min
70
-
-
-
-
10
10
5
0
0
0
5
70
60
0
60
60
50
0
0
20
0
5
25
-
-
10
70ns
Max
40k
70
70
25
70
-
-
-
5
5
5
-
40k
-
-
-
-
-
-
5
-
-
-
-
25
40k
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
5
Revision 0.5
Jul. 2006
FIDELIX [ FIDELIX ]
