Chapter 14
Low Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the V
DD
pin
and generates a reset when the V
DD
voltage falls to the LVI trip (LVI
TRIP
) voltage.
14.2 Features
Features of the LVI module include the following:
• Selectable LVI trip voltage
• Selectable LVI circuit disable
14.3 Functional Description
shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module
contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to
monitor V
DD
voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which V
DD
level the
LVI module should take actions.
The LVI module generates one output signal:
LVI Reset
— an reset signal will be generated to reset the CPU when V
DD
drops to below the set trip
point.
V
DD
LVID
V
DD
> LVI
TRIP
= 0
LOW V
DD
DETECTOR
V
DD
< LVI
TRIP
= 1
LVI RESET
LVIT1
LVIT0
Figure 14-1. LVI Module Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
127
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
