Chapter 15
Break Module (BREAK)
15.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
15.2 Features
Features of the break module include the following:
• Accessible I/O registers during the break Interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
15.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The
program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a one to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal operation.
shows the
structure of the break module.
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
BKPT
(TO SIM)
Figure 15-1. Break Module Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
129
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
